The present invention relates to a non-volatile memory cell, that uses a floating gate formed in a cavity for the storage of charges. More particularly, the present invention relates to such a non-volatile memory cell in which two floating gates are formed, and is capable of bi-directionally storing and reading a plurality of bits in a single cell and an array of such cells, and a method of manufacturing.
Uni-directional read/program non-volatile memory cells using floating gate for storage are well known in the art. See for example, U.S. Pat. No. 5,029,130. Typically, each of these types of memory cells uses a conductive floating gate to store one bit, i.e. either the floating gate stores charges or it does not. The charges stored on a floating gate control the conduction of charges in a channel of a transistor. In a desire to increase the storage capacity of such non-volatile memory cells, the floating gate of such memory cell is programmed to store some charges, with the different amount of charges stored being determinative of the different states of the cell, thereby causing a plurality of bits to be stored in a single cell. The problem with programming a cell to one of a multilevel state and then reading such a state is that the amount of charge stored on the floating gate differentiating one state from another must be very carefully controlled. Further, in the unidirectional read/program non-volatile memory cell of the prior art, the floating gate has been made by a lithographic process involving masking steps and the like, resulting in a xe2x80x9clargexe2x80x9d structure.
In an article entitled xe2x80x9cQuantum-well Memory Device (QWMD) with Extremely Good Charge Retentionxe2x80x9d by Z. Krivokapic et al., published by IEEE in 2002, the authors described a device using floating gates as quantum wells. This however, is very different from a non-volatile memory cell with spaced apart regions and a channel therebetween for the conduction of charges.
Bi-directional read/program non-volatile memory cells capable of storing a plurality of bits in a single cell are also well known in the art. See, for example, U.S. Pat. No. 6,011,725. Typically, these types of memory cells use an insulating trapping material, such as silicon nitride, which is between two other insulation layers, such as silicon dioxide, to trap charges. The charges are trapped near the source/drain also to control the conduction of charges in a channel of a transistor. The cell is read in one direction to determine the state of charges trapped near one of the source/drain regions, and is read in the opposite direction to determine the state of charges trapped near the other source/drain region. Hence, these cells are read and programmed bi-directionally. The problem with these types of cells is that to erase, holes or charges of the opposite conductivity must also be xe2x80x9cprogrammedxe2x80x9d or injected into the trapping material at precisely the same location where the programming charges were initially trapped in order to xe2x80x9cneutralizexe2x80x9d the programming charges. Since the programming charges and the erase charges are injected into a non-conductive trapping material, the charges do not move as in a conductive material. Therefore, if there is any error in injecting the erase charges to the location of the programming charges, the erase charges will not neutralize the programming charges, and the cell will not be completely erased. Moreover, to inject the erase charges, the cell must be erased bi-directionally, thereby increasing the time required for erasure of one cell.
Hence there is a need for a non-volatile memory cell and array that overcomes these problems.
In the present invention, a non-volatile memory cell comprises a substantially single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the floating gate having generally a triangular shape. A gate electrode is capacitively coupled to the floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region.
The present invention also relates to a bi-directional read/program non-volatile memory cell having two floating gates, each having a generally triangular shape, and an array of the foregoing described non-volatile memory cells, and a method of making the non-volatile memory cell and the array.